1. Field of the Invention
The present invention relates to a semiconductor device having a buried field-shield element isolation structure or a buried gate electrode and a method of fabricating the same.
2. Description of the Related Art
As the miniaturization of elements advances in semiconductor devices such as LSIs, a field-shield element isolation technology by which a shield-plate electrode is buried in a silicon oxide film has been proposed as an element isolation technology replacing a LOCOS process, in order to decrease the size transformation errors. As field-shield element isolation structures formed by this element isolation technology, a so-called planar structure formed on a silicon substrate and a trench structure in which an element isolation region is formed in a substrate are being studied. An example of an element isolation technology for forming a planar field-shield element isolation structure is disclosed in Japanese Patent Laid-Open No. 6-291181. An example of an element isolation technology for forming a trench field-shield element isolation structure is disclosed in Japanese Patent Laid-Open No. 5-109886.
In a planar field-shield element isolation structure, a shield-gate oxide film and a shield-plate electrode are patterned on a silicon substrate. A cap oxide film and a side-wall protective film are formed to cover the shield-plate electrode.
In a trench field-shield element isolation structure, a shield-plate electrode surrounded by a shield-gate oxide film and a cap oxide film is buried in a trench formed in a silicon substrate.
Note that a semiconductor device in which an element isolation structure is not a field-shield element isolation structure but is formed by burying a trench formed in a silicon substrate with an insulator is disclosed in Japanese Patent Laid-Open No. 1-245540. In this Japanese Patent Laid-Open No. 1-245540, a well is formed by doping an impurity into a silicon substrate in which an insulator is buried in a trench.
In the field-shield element isolation structure disclosed in Japanese Patent Laid-Open No. 6-291181, after the cap oxide film and the side-wall protective film for covering the shield-plate electrode are formed, an impurity is ion-implanted into this field-shield element isolation structure. Consequently, an impurity diffusion layer is formed in the silicon substrate immediately below the shield-gate oxide film, and the ion-implanted impurity distributes in a deep portion of the silicon substrate in an element formation region. Accordingly, the element isolation capability can be improved by the impurity diffusion layer without adversely affecting an element such as a transistor formed in the element formation region.
Also, in the field-shield element isolation structure disclosed in Japanese Patent Laid-Open No. 5-109886, both a shield-plate electrode formed in a p-well region and a shield-plate electrode formed in an n-well region are of an n type. Therefore, in the p-well region, the work function difference between the n-type shield-plate electrode and the p-well diffusion layer below the electrode is large. This decreases the threshold voltage of a parasitic transistor formed in that portion. To avoid this, in the structure disclosed in Japanese Patent Laid-Open No. 5-109886, an enhancement p-type diffusion layer is formed around the trench in the p-well region.
In the above trench structure, however, it is necessary to perform oblique ion implantation or the like to particularly reliably dope a p-type impurity into the side walls of the trench to form the enhancement p-type diffusion layer. This complicates the fabrication process.
On the other hand, Japanese Patent Laid-Open No. 3-290950 discloses that the problem of the work function difference in the p-well region is solved by the use of an n-type shield-plate electrode in the n-well region and a p-type shield plate electrode in the p-well region, and that this obviates the need for enhancement impurity implantation in the p-well region. Unfortunately, the field-shield element isolation structure disclosed in this Japanese Patent Laid-Open No. 3-290950 is not a buried type trench structure but a conventional planar field-shield element isolation structure formed on a substrate.